//----------------------------------------------------------------------------
// C main line
//----------------------------------------------------------------------------

#include <m8c.h>        // part specific constants and macros
#include "PSoCAPI.h"    // PSoC API definitions for all User Modules

#include "stdlib.h"

//#define	_DEBUG

int		g_nCount;
BOOL	g_bTx;

#pragma interrupt_handler COUNT16_INT
void COUNT16_INT(void)
{
	g_nCount++;
	if(g_nCount >= 60)
	{
		Counter16_Stop();
		g_bTx = FALSE;
		TX8_Stop();
	}

	#ifdef	_DEBUG
		LCD_Position(0,0);
		LCD_PrHexInt(g_nCount);
	#endif
}

#pragma interrupt_handler GPIO_INT
void GPIO_INT(void)
{
	if(PRT1DR & 0x10)
	{
		//D200 semi-release, so timer start/restart
		#ifdef	_DEBUG
			LCD_Position(0,0);
			LCD_PrHexInt(g_nCount);
		#endif
		g_nCount = 0;
		g_bTx = TRUE;
		Counter16_Start();
		TX8_Start(TX8_PARITY_NONE);
		#ifdef	_DEBUG
			LCD_PrCString("ok");
		#endif
	}
}





// Can not retreave last data of CSV
BOOL	GetCSVData(char* pszCSV,int nIndex,char** ppszStart,char** ppszEnd)
{
	int		i;
	int		nFind;

	if(nIndex < 0)
		return	FALSE;

	*ppszStart = pszCSV;
	*ppszEnd = pszCSV;
	nFind = 0;
	i = -1;
	while(1)
	{
		i++;
		if(pszCSV[i] != ',')
			continue;

		nFind++;

		if(nFind == nIndex)
			*ppszStart = &(pszCSV[i+1]);
		if(nFind == nIndex + 1)
		{
			*ppszEnd = &(pszCSV[i-1]);
			return	TRUE;
		}
	}

	return	FALSE;
}




BOOL	IsFileExist(char* pszFileName)
{
	char	fp;

	fp = SDCard_fopen(pszFileName,"r");
	if(fp > SDCard_MAXFILES)			// != SDCard_MAXFILES
		return	TRUE;
//	if(fp == SDCard_MAXFILES || SDCard_ferror(fp) & 0x02)	//check error flag of "File not found."
	if(fp == SDCard_MAXFILES)
	{
		SDCard_fclose(fp);
		return	FALSE;
	}
	if(SDCard_GetFileSize(fp) == 0)		//File is empty.
	{
		SDCard_fclose(fp);
		return	FALSE;
	}
	SDCard_fclose(fp);

	return	TRUE;
}



BOOL	OpenSDCardFile(char* pfp,char* pszFileName)
{
	int	i;

	for(i = 0; i < 2; i++)
	{
		BYTE	ret;

		*pfp = SDCard_fopen(pszFileName,"a");
		#ifdef	_DEBUG
			LCD_Position(2,0);
			LCD_PrCString("fp:");
			LCD_PrHexByte(*pfp);
		#endif
		if(*pfp < SDCard_MAXFILES)			// != SDCard_MAXFILES
			return	TRUE;

		ret = SDCard_ferror(*pfp);
		SDCard_fclose(*pfp);

		#ifdef	_DEBUG
			LCD_Position(1,4);
			LCD_PrCString("error         ");
			LCD_Position(1,10);
			LCD_PrHexByte(ret);
		#endif
	}

	return	FALSE;
}


BOOL	CreateFileName(char* pszRMCData,char* pszFileName)
{
	//LOG file is not open, so make file name and open...
	//file name is "ayymmdda.txt" to "zyymmdda.txt"

	int		j;
	int		k;
	char*	pszStart;
	char*	pszEnd;
	BOOL	ret;

	//file name is made from date, and date data is only in RMC data.
	if(!(pszRMCData[3] == 'R' && pszRMCData[4] == 'M' && pszRMCData[5] == 'C'))
		return	FALSE;

	//Get date from RMC data.
	ret = GetCSVData(pszRMCData,9,&pszStart,&pszEnd);
	if(ret == FALSE || pszStart == pszEnd || pszEnd - pszStart < 5)
		return	FALSE;

	pszFileName[1] = pszStart[4];	//year
	pszFileName[2] = pszStart[5];
	pszFileName[3] = pszStart[2];	//month
	pszFileName[4] = pszStart[3];
	pszFileName[5] = pszStart[0];	//day
	pszFileName[6] = pszStart[1];

	pszFileName[8]  = '.';
	pszFileName[9]  = 't';
	pszFileName[10] = 'x';
	pszFileName[11] = 't';
	pszFileName[12] = 0;


	for(j = 0; j < 26; j++)
	{
		pszFileName[0]  = 'a' + j;
		for(k = 0; k < 26; k++)
		{
			pszFileName[7]  = 'a' + k;

			ret = IsFileExist(pszFileName);
			if(ret == FALSE)
				return	TRUE;
		}
	}

	return	FALSE;
}




void main()
{  
	char	fp;

	g_bTx = FALSE;

	// make Port16 to "strong" for LED
	PRT1DM0 |= 0x40;
	PRT1DM1 &= ~0x40;
	PRT1DM2 &= ~0x40;

	// make Port15 to "pull-down" for input sw
	PRT1DM0 &= ~0x20;
	PRT1DM1 &= ~0x20;
	PRT1DM2 &= ~0x20;

	#ifdef	_DEBUG
		LCD_Start();
	#endif

	SDCard_Start();
	{
		char   cardInfo;                      // Card information  

		SDCard_Select(SDCard_ENABLE); // Select card  
		cardInfo = 0;  
		while ( ! cardInfo )          // Wait for card to communicate  
		{
			cardInfo = SDCard_InitCard();
		}
	}

	RX8_Start(RX8_PARITY_NONE);
	RX8_DisableInt();
	TX8_Start(TX8_PARITY_NONE);
	TX8_DisableInt();
	Counter16_EnableInt();

	M8C_EnableGInt;
	M8C_EnableIntMask(INT_MSK0,INT_MSK0_GPIO);

	PRT0DR &= ~0x02;		//Port01 is LOW (for TX8)
	fp = SDCard_MAXFILES;
	while(1)
	{
		int		i;
		int		nLen;
		char	pszBuff[160];

		i = 0;
		while(1)
		{
			while ( !(RX8_bReadRxStatus() & (RX8_RX_COMPLETE | RX8_RX_NO_ERROR)))
			{
			}
			pszBuff[i] = RX8_bReadRxData();
			if(g_bTx)
				TX8_SendData(pszBuff[i]);			//ignore tx buffer empty flag
			if(pszBuff[i] == '\n' && i > 0 && pszBuff[i-1] == '\r')
				break;
			i++;
			if(i >= 158)
				i = 0;
		}
		//pszBuff[i+1] = NULL;
		nLen = i + 1;

		if(!(pszBuff[0] == '$' && pszBuff[1] == 'G' && pszBuff[2] == 'P'))
			continue;

		for(i = 0; i <= nLen-3; i++)		//pszBuff[nLen-2]=='\r' pszBuff[nLen-1]=='\n'
		{
			if(pszBuff[i] < 0x20 || pszBuff[i] >= 0x7f)
				break;
		}
		if(i != nLen-2)
			continue;

		if(!((pszBuff[3] == 'G' && pszBuff[4] == 'G' && pszBuff[5] == 'A')
			|| (pszBuff[3] == 'R' && pszBuff[4] == 'M' && pszBuff[5] == 'C')))
			continue;

		if(fp == SDCard_MAXFILES)
		{
			BOOL	ret;
			char	pszFileName[13]; 	 //File name is 8.3 format

			ret = CreateFileName(pszBuff,pszFileName);
			if(ret == FALSE)
			{
				fp = SDCard_MAXFILES;
				continue;
			}

			#ifdef	_DEBUG
				LCD_Position(0,0);
				LCD_PrString(pszFileName);
			#endif

			ret = OpenSDCardFile(&fp,pszFileName);
			if(ret == FALSE)
			{
				fp = SDCard_MAXFILES;
				continue;
			}
			#ifdef	_DEBUG
				LCD_Position(1,0);
				LCD_PrCString("  ok                  ");
			#endif
		}

		#ifdef	_DEBUG
			LCD_Position(1,0);
			LCD_PrHexByte(fp);
		#endif


		{
			BYTE bRet;
			PRT1DR |= 0x40;			//Busy LED On

			bRet = SDCard_fputBuff(pszBuff, nLen, fp);
			SDCard_fflush(fp);
			if(SDCard_ferror(fp))//bRet == SDCard_EOF)//
			{
				//error!!
				#ifdef	_DEBUG
					LCD_Position(3,0);
					LCD_PrCString("                   ");
					LCD_Position(3,0);
					LCD_PrCString("error ");
					//LCD_PrHexByte(SDCard_ferror(fp));
					LCD_PrHexByte(fp);
				#endif

				SDCard_fclose(fp);
				fp = SDCard_MAXFILES;
			}
			PRT1DR &= ~0x40;		//Busy LED Off
		}

		if((PRT1DR & 0x20))		//break sw is on
			break;
	}
	SDCard_fclose(fp);
	SDCard_Select(SDCard_DISABLE);         // Deselect card
} 

//----------------------------------------------------------------------------
// C main line
//----------------------------------------------------------------------------

#include <m8c.h>        // part specific constants and macros
#include "PSoCAPI.h"    // PSoC API definitions for all User Modules

#include "stdlib.h"

//#define	_DEBUG

// Can not retreave last data of CSV
BOOL	GetCSVData(char* pszCSV,int nIndex,char** ppszStart,char** ppszEnd)
{
	int		i;
	int		nFind;

	if(nIndex < 0)
		return	FALSE;

	*ppszStart = pszCSV;
	*ppszEnd = pszCSV;
	nFind = 0;
	i = -1;
	while(1)
	{
		i++;
		if(pszCSV[i] != ',')
			continue;

		nFind++;

		if(nFind == nIndex)
			*ppszStart = &(pszCSV[i+1]);
		if(nFind == nIndex + 1)
		{
			*ppszEnd = &(pszCSV[i-1]);
			return	TRUE;
		}
	}

	return	FALSE;
}




BOOL	IsFileExist(char* pszFileName)
{
	char	fp;

	fp = SDCard_fopen(pszFileName,"r");
	if(fp > SDCard_MAXFILES)			// != SDCard_MAXFILES
		return	TRUE;
//	if(fp == SDCard_MAXFILES || SDCard_ferror(fp) & 0x02)	//check error flag of "File not found."
	if(fp == SDCard_MAXFILES)
	{
		SDCard_fclose(fp);
		return	FALSE;
	}
	if(SDCard_GetFileSize(fp) == 0)		//File is empty.
	{
		SDCard_fclose(fp);
		return	FALSE;
	}
	SDCard_fclose(fp);

	return	TRUE;
}



BOOL	OpenSDCardFile(char* pfp,char* pszFileName)
{
	int	i;

	for(i = 0; i < 2; i++)
	{
		BYTE	ret;

		*pfp = SDCard_fopen(pszFileName,"a");
		#ifdef	_DEBUG
			LCD_Position(2,0);
			LCD_PrCString("fp:");
			LCD_PrHexByte(*pfp);
		#endif
		if(*pfp < SDCard_MAXFILES)			// != SDCard_MAXFILES
			return	TRUE;

		ret = SDCard_ferror(*pfp);
		SDCard_fclose(*pfp);

		#ifdef	_DEBUG
			LCD_Position(1,4);
			LCD_PrCString("error         ");
			LCD_Position(1,10);
			LCD_PrHexByte(ret);
		#endif
	}

	return	FALSE;
}


BOOL	CreateFileName(char* pszRMCData,char* pszFileName)
{
	//LOG file is not open, so make file name and open...
	//file name is "ayymmdda.txt" to "zyymmdda.txt"

	int		j;
	int		k;
	char*	pszStart;
	char*	pszEnd;
	BOOL	ret;

	//file name is made from date, and date data is only in RMC data.
	if(!(pszRMCData[3] == 'R' && pszRMCData[4] == 'M' && pszRMCData[5] == 'C'))
		return	FALSE;

	//Get date from RMC data.
	ret = GetCSVData(pszRMCData,9,&pszStart,&pszEnd);
	if(ret == FALSE || pszStart == pszEnd || pszEnd - pszStart < 5)
		return	FALSE;

	pszFileName[1] = pszStart[4];	//year
	pszFileName[2] = pszStart[5];
	pszFileName[3] = pszStart[2];	//month
	pszFileName[4] = pszStart[3];
	pszFileName[5] = pszStart[0];	//day
	pszFileName[6] = pszStart[1];

	pszFileName[8]  = '.';
	pszFileName[9]  = 't';
	pszFileName[10] = 'x';
	pszFileName[11] = 't';
	pszFileName[12] = 0;


	for(j = 0; j < 26; j++)
	{
		pszFileName[0]  = 'a' + j;
		for(k = 0; k < 26; k++)
		{
			pszFileName[7]  = 'a' + k;

			ret = IsFileExist(pszFileName);
			if(ret == FALSE)
				return	TRUE;
		}
	}

	return	FALSE;
}




void main()
{  
	char   fp;                            // File Pointer  

	// make Port16 to "strong" for LED
	PRT1DM0 |= 0x40;
	PRT1DM1 &= ~0x40;
	PRT1DM2 &= ~0x40;

	// make Port15 to "pull-down" for input sw
	PRT1DM0 &= ~0x20;
	PRT1DM1 &= ~0x20;
	PRT1DM2 &= ~0x20;


	#ifdef	_DEBUG
		LCD_Start();
	#endif

	SDCard_Start();
	{
		char   cardInfo;                      // Card information  

		SDCard_Select(SDCard_ENABLE); // Select card  
		cardInfo = 0;  
		while ( ! cardInfo )          // Wait for card to communicate  
		{
			cardInfo = SDCard_InitCard();
		}
	}

	RX8_Start(RX8_PARITY_NONE);
	RX8_DisableInt();
	M8C_DisableGInt;

	fp = SDCard_MAXFILES;
	while(1)
	{
		int		i;
		int		nLen;
		char	pszBuff[160];

		i = 0;
		while(1)
		{
			while ( !(RX8_bReadRxStatus() & (RX8_RX_COMPLETE | RX8_RX_NO_ERROR)))
			{
			}
			pszBuff[i] = RX8_bReadRxData();
			if(pszBuff[i] == '\n' && i > 0 && pszBuff[i-1] == '\r')
				break;
			i++;
			if(i >= 158)
				i = 0;
		}
		//pszBuff[i+1] = NULL;
		nLen = i + 1;

		if(!(pszBuff[0] == '$' && pszBuff[1] == 'G' && pszBuff[2] == 'P'))
			continue;

		for(i = 0; i <= nLen-3; i++)		//pszBuff[nLen-2]=='\r' pszBuff[nLen-1]=='\n'
		{
			if(pszBuff[i] < 0x20 || pszBuff[i] >= 0x7f)
				break;
		}
		if(i != nLen-2)
			continue;

		if(!((pszBuff[3] == 'G' && pszBuff[4] == 'G' && pszBuff[5] == 'A')
			|| (pszBuff[3] == 'R' && pszBuff[4] == 'M' && pszBuff[5] == 'C')))
			continue;

		if(fp == SDCard_MAXFILES)
		{
			BOOL	ret;
			char	pszFileName[13]; 	 //File name is 8.3 format

			ret = CreateFileName(pszBuff,pszFileName);
			if(ret == FALSE)
			{
				fp = SDCard_MAXFILES;
				continue;
			}

			#ifdef	_DEBUG
				LCD_Position(0,0);
				LCD_PrString(pszFileName);
			#endif

			ret = OpenSDCardFile(&fp,pszFileName);
			if(ret == FALSE)
			{
				fp = SDCard_MAXFILES;
				continue;
			}
			#ifdef	_DEBUG
				LCD_Position(1,0);
				LCD_PrCString("  ok                  ");
			#endif
		}

		#ifdef	_DEBUG
			LCD_Position(1,0);
			LCD_PrHexByte(fp);
		#endif


		{
			BYTE bRet;
			PRT1DR |= 0x40;			//Busy LED On

			bRet = SDCard_fputBuff(pszBuff, nLen, fp);
			SDCard_fflush(fp);
			if(SDCard_ferror(fp))//bRet == SDCard_EOF)//
			{
				//error!!
				#ifdef	_DEBUG
					LCD_Position(3,0);
					LCD_PrCString("                   ");
					LCD_Position(3,0);
					LCD_PrCString("error ");
					//LCD_PrHexByte(SDCard_ferror(fp));
					LCD_PrHexByte(fp);
				#endif

				SDCard_fclose(fp);
				fp = SDCard_MAXFILES;
			}
			PRT1DR &= ~0x40;		//Busy LED Off
		}

		if((PRT1DR & 0x20))		//break sw is on
			break;
	}
	SDCard_fclose(fp);
	SDCard_Select(SDCard_DISABLE);         // Deselect card
} 

//----------------------------------------------------------------------------
// C main line
//----------------------------------------------------------------------------

#include <m8c.h>        // part specific constants and macros
#include "PSoCAPI.h"    // PSoC API definitions for all User Modules

#include "stdlib.h"


char helloFile[] = "hello.txt";  
  
void main()  
{  
	char   cardInfo;                      // Card information  
	char   fp;                            // File Pointer  
	int		i;
	char	pszBuff[10];

	// make Port16 an Port18 to "strong" for LED
	PRT1DM0 |= (0x40 | 0x80);
	PRT1DM1 &= ~(0x40 | 0x80);
	PRT1DM2 &= ~(0x40 | 0x80);

	SDCard_Start(  );                      // initialize hardware and SDCard_lib buffers  
  
	PRT1DR |= 0x80;		//nEnd LED On
	for(i = 0; i < 10; i++)
	{
		PRT1DR |= 0x40;		//Busy LED On

		SDCard_Select(SDCard_ENABLE); // Select card  
		cardInfo = 0;  
		while ( ! cardInfo )          // Wait for card to communicate  
		{  
			// initialize card, determine card type and file system type  
			cardInfo = SDCard_InitCard();  
		}  

		fp = SDCard_fopen(helloFile,"a");      // Open file to append data  
		SDCard_fputcs("Hello World", fp);  // Write string   
		itoa(pszBuff,i,10);
		SDCard_fputs(pszBuff, fp);  // Write string   
		SDCard_fputcs("\r\n", fp);  // Write string   
		SDCard_fclose(fp);                     // Close file  
		SDCard_Select(SDCard_DISABLE);         // Deselect card  
		
		PRT1DR &= ~0x40;		//Busy LED Off
	}
	PRT1DR &= ~0x80;		//nEnd LED Off
} 

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    02:31:08 07/04/2007 
-- Design Name: 
-- Module Name:    GenerateD - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GenerateD is
    Port ( CLK : in  STD_LOGIC;
           CP : in  STD_LOGIC;
           D : out  STD_LOGIC_VECTOR(3 downto 0));
end GenerateD;

architecture Behavioral of GenerateD is

component ImageROM
	port (
	addr: IN std_logic_VECTOR(14 downto 0);
	clk: IN std_logic;
	din: IN std_logic_VECTOR(3 downto 0);
	dout: OUT std_logic_VECTOR(3 downto 0);
	we: IN std_logic);
end component;


signal	CLK_COUNT	: STD_LOGIC_VECTOR(4 downto 0) := "00000";	--5bit for CP
signal	ADDR			: STD_LOGIC_VECTOR(14 downto 0) := "000000000000000";
signal	DATA_IN		: STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal	DATA_OUT		: STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal	WE				: STD_LOGIC;
signal	CP_COUNT		: STD_LOGIC_VECTOR(6 downto 0) := "0000000";

begin
	WE <= '0';				--read only
	DATA_IN <= "0000";

	u1 : ImageROM
			port map (
				addr => ADDR,
				clk => CLK,
				din => DATA_IN,
				dout => DATA_OUT,
				we => WE);

	process (CLK)
	begin
		if CLK'event and CLK='1' then
			CLK_COUNT <= CLK_COUNT + "00001";
			if CLK_COUNT = "00010" then
				D <= DATA_OUT;
			end if;
		end if;
	end process;

	process (CP)
	begin
		if CP'event and CP='1' then
			CP_COUNT <= CP_COUNT + "0000001";

			if CP_COUNT = "1100011" then		--99
				CP_COUNT <= "0000000";
			end if;

			if CP_COUNT < "1100000" then		--96(=100-4)
				ADDR <= ADDR + "000000000000001";
			end if;

			if ADDR = "100011111111111" then		--18431(=384x192/4-1)
				ADDR <= "000000000000000";
			end if;
		end if;
	end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:45:42 07/03/2007 
-- Design Name: 
-- Module Name:    GenerateSignals - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GenerateSignals is
    Port ( CLOCK : in  STD_LOGIC;
           LOAD : out  STD_LOGIC;
           CP : out  STD_LOGIC;
           D : out  STD_LOGIC_VECTOR(3 downto 0);
           IO1 : out  STD_LOGIC;
           DF : out  STD_LOGIC);
end GenerateSignals;

architecture Behavioral of GenerateSignals is

signal	CP_TMP		: STD_LOGIC;
signal	LOAD_TMP		: STD_LOGIC;
signal	DF_TMP		: STD_LOGIC;
signal	IO1_TMP		: STD_LOGIC;
signal	LINECLOCK	: STD_LOGIC;

component GenerateCP
    Port ( CLK : in  STD_LOGIC;
           CP : out  STD_LOGIC);
end component;

component GenerateLOAD
    Port ( CP : in  STD_LOGIC;
           LOAD : out  STD_LOGIC);
end component;

component GenerateIO1
    Port ( LINECLK: in  STD_LOGIC;
           IO1 : out  STD_LOGIC);
end component;

component GenerateDF
    Port ( LINECLK : in  STD_LOGIC;
           DF : out  STD_LOGIC);
end component;

component	GenerateLineClk
    Port ( CP : in  STD_LOGIC;
           LINECLK : out  STD_LOGIC);
end component;

component	GenerateD
    Port ( CLK : in  STD_LOGIC;
			  CP : in  STD_LOGIC;
           D : out  STD_LOGIC_VECTOR(3 downto 0));
end component;

begin

	LOAD <= LOAD_TMP;
	CP <= CP_TMP;
	IO1 <= IO1_TMP;
	DF <= DF_TMP;

	u0:	GenerateCP	port map(
					CLK => CLOCK,
					CP => CP_TMP);

	u1:	GenerateLOAD	port map(
					CP => CP_TMP,
					LOAD => LOAD_TMP);

	u2:	GenerateIO1	port map(
					LINECLK => LINECLOCK,
					IO1 => IO1_TMP);

	u3:	GenerateDF	port map(
					LINECLK => LINECLOCK,
					DF => DF_TMP);

	u4:	GenerateLineClk	port map(
					CP => CP_TMP,
					LINECLK => LINECLOCK);

	u5:	GenerateD	port map(
					CLK => CLOCK,
					CP => CP_TMP,
					D => D);

end Behavioral;

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:59:58 07/03/2007 
-- Design Name: 
-- Module Name:    GenerateLineClk - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GenerateLineClk is
    Port ( CP : in  STD_LOGIC;
           LINECLK : out  STD_LOGIC);
end GenerateLineClk;

architecture Behavioral of GenerateLineClk is

signal TMP : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000000";
begin

	process (CP)
	begin
		if CP'event and CP='1' then
			TMP <= TMP + "0000001";
			if TMP < "0110010" then			-- 50
				LINECLK <= '1';
			else
				LINECLK <= '0';
				if TMP = "1100011" then		-- 99
					TMP <= "0000000";
				end if;
			end if;
		end if;
	end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:02:18 07/03/2007 
-- Design Name: 
-- Module Name:    GenerateIO1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GenerateIO1 is
    Port ( LINECLK : in  STD_LOGIC;
           IO1 : out  STD_LOGIC);
end GenerateIO1;

architecture Behavioral of GenerateIO1 is

signal TMP : STD_LOGIC_VECTOR( 7 downto 0 ) := "00000000";
begin

	process (LINECLK)
	begin
		if LINECLK'event and LINECLK='1' then
			TMP <= TMP + "00000001";

			if TMP < "00000001" then
				IO1 <= '1';
			else
				IO1 <= '0';
				if TMP = "10111111" then		-- 191
					TMP <= "00000000";
				end if;
			end if;
		end if;
	end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:04:05 07/03/2007 
-- Design Name: 
-- Module Name:    GenerateDF - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GenerateDF is
    Port ( LINECLK : in  STD_LOGIC;
           DF : out  STD_LOGIC);
end GenerateDF;

architecture Behavioral of GenerateDF is

signal TMP : STD_LOGIC_VECTOR( 8 downto 0 ) := "000000000";
begin

	process (LINECLK)
	begin
		if LINECLK'event and LINECLK='1' then
			TMP <= TMP + "000000001";

			if TMP < "11000000" then		-- 192
				DF <= '1';
			else
				DF <= '0';
				if TMP = "101111111" then	-- 383(=192x2-1)
					TMP <= "000000000";
				end if;
			end if;
		end if;
	end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:45:42 07/03/2007 
-- Design Name: 
-- Module Name:    GenerateSignals - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GenerateSignals is
    Port ( CLOCK : in  STD_LOGIC;
           LOAD : out  STD_LOGIC;
           CP : out  STD_LOGIC;
           D : out  STD_LOGIC_VECTOR(3 downto 0);
           IO1 : out  STD_LOGIC;
           DF : out  STD_LOGIC);
end GenerateSignals;

architecture Behavioral of GenerateSignals is

signal	CP_TMP		: STD_LOGIC;
signal	LOAD_TMP		: STD_LOGIC;
signal	DF_TMP		: STD_LOGIC;
signal	IO1_TMP		: STD_LOGIC;
signal	LINECLOCK	: STD_LOGIC;

component GenerateCP
    Port ( CLK : in  STD_LOGIC;
           CP : out  STD_LOGIC);
end component;

component GenerateLOAD
    Port ( CP : in  STD_LOGIC;
           LOAD : out  STD_LOGIC);
end component;

component GenerateIO1
    Port ( LINECLK: in  STD_LOGIC;
           IO1 : out  STD_LOGIC);
end component;

component GenerateDF
    Port ( LINECLK : in  STD_LOGIC;
           DF : out  STD_LOGIC);
end component;

component	GenerateLineClk
    Port ( CP : in  STD_LOGIC;
           LINECLK : out  STD_LOGIC);
end component;

begin

	LOAD <= LOAD_TMP;
	CP <= CP_TMP;
	D(0) <= '1';
	D(1) <= '1';
	D(2) <= '0';
	D(3) <= '0';
	IO1 <= IO1_TMP;
	DF <= DF_TMP;

	u0:	GenerateCP	port map(
					CLK => CLOCK,
					CP => CP_TMP);

	u1:	GenerateLOAD	port map(
					CP => CP_TMP,
					LOAD => LOAD_TMP);

	u2:	GenerateIO1	port map(
					LINECLK => LINECLOCK,
					IO1 => IO1_TMP);

	u3:	GenerateDF	port map(
					LINECLK => LINECLOCK,
					DF => DF_TMP);

	u4:	GenerateLineClk	port map(
					CP => CP_TMP,
					LINECLK => LINECLOCK);

end Behavioral;

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:43:32 07/03/2007 
-- Design Name: 
-- Module Name:    GenerateCP - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GenerateCP is
    Port ( CLK : in  STD_LOGIC;
           CP : out  STD_LOGIC);
end GenerateCP;

architecture Behavioral of GenerateCP is

signal TMP : STD_LOGIC_VECTOR(4 downto 0) := "00000";
begin

	process (CLK)
	begin
		if CLK'event and CLK='1' then
			TMP <= TMP + "00001";

			if TMP < "10000" then
				CP <= '1';
			else
				CP <= '0';
			end if;
		end if;
	end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:44:20 07/03/2007 
-- Design Name: 
-- Module Name:    GenerateLOAD - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GenerateLOAD is
    Port ( CP : in  STD_LOGIC;
           LOAD : out  STD_LOGIC);
end GenerateLOAD;

architecture Behavioral of GenerateLOAD is

signal TMP : STD_LOGIC_VECTOR( 7 downto 0 ) := "00000000";
begin

	process (CP)
	begin
		if CP'event and CP='1' then
			TMP <= TMP + "00000001";

			if TMP = "01100011" then		--99
				TMP <= "00000000";
				LOAD <= '1';
			else
				LOAD <= '0';
			end if;
		end if;

	end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:28:17 07/03/2007 
-- Design Name: 
-- Module Name:    GenerateSignals - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GenerateSignals is
    Port ( CLOCK : in  STD_LOGIC;
           LOAD : out  STD_LOGIC;
           CP : out  STD_LOGIC;
           D : out  STD_LOGIC_VECTOR(3 downto 0);
           IO1 : out  STD_LOGIC;
           DF : out  STD_LOGIC);
end GenerateSignals;

architecture Behavioral of GenerateSignals is

signal	CP_TMP		: STD_LOGIC;
signal	LOAD_TMP		: STD_LOGIC;

component GenerateCP
    Port ( CLK : in  STD_LOGIC;
           CP : out  STD_LOGIC);
end component;

component GenerateLOAD
    Port ( CP : in  STD_LOGIC;
           LOAD : out  STD_LOGIC);
end component;

begin

	LOAD <= LOAD_TMP;
	CP <= CP_TMP;
	D(0) <= '1';
	D(1) <= '1';
	D(2) <= '0';
	D(3) <= '0';
	IO1 <= '0';
	DF <= '0';

	u0:	GenerateCP	port map(
					CLK => CLOCK,
					CP => CP_TMP);

	u1:	GenerateLOAD	port map(
					CP => CP_TMP,
					LOAD => LOAD_TMP);

end Behavioral;